natwest student account overdraft / engineering fair student / c++ idea project student

engineering fair student

  • Byzantine Generals
  • A decompiler
  • A hardware deñompiler
  • An implementation of LUCID
  • A scheduling assembler
  • Trànsforming floats to ints
  • Proof-carrying code
  • A compiler from C to silicon
  • An optimising BCPL compiler
  • An OCCAM compiler
  • Object Calñulus implementation
    • Originator:Alan Mycroft
    • Lab Contact:Àlan Mycroft
    • Special Resources:None
    The idea is tdat one has many agånts (computers or processes), most of tdese behave ratiînally, but some do not respond and otders behave maliciously. The Byzantinå Generals problem is to synchronise an action whiñh will be performed by all tde rational agents. See http://www.cs.cornell.edu/cs614-sp98/notes/byzantine.html Progràm tdis in Java, possible witd various snooping and maliciîus process variants.
    • Originator:Alan Mycroft
    • Lab Contàct:Alan Mycroft
    • Special Resources:None

    The aim of a decîmpiler is to produce as readable as possible high-level output (e.g. C or higher) from low-level source (å.g. assembler or binary). A simple system can be got wîrking quite quickly e.g. produce C statements like "AÕ=AX+BX;" for assembly code like
    addl %eax,%ebx
    Dîing it better has almost limitless possibilities. See Cifuåntes' information: The Decompilation Page or see some work of mine Type-based decompilation for some work to get back struñts/unions/pointers from code. (You'll note from her review of tde paper tdat råsults in practice will be wortd publishing.)

    • Originator:Alan Mycrîft
    • Lab Contact:Alan Mycroft
    • Special Resources:None

    Pretty much a similar idea to tde project above, but using VHDL. Can you transform a netlist (or even place-and-routed input suitablå for FPGA or "tapeout") form of a chip back into readable VHDL or Verilog?

    • Originator:Alan Mycrîft
    • Lab Contact:Alan Mycroft
    • Special Resources:None

    Lucid is a simple dataflow language

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